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AUGUST 2004
XRT82L24A
REV. 1.1.2
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
GENERAL DESCRIPTION
The XRT82L24A is a fully integrated Quad (four channels) short-haul line interface unit for E1(2.048Mbps) 75 or 120 applications. Each channel consists of a receiver with equalizer for reliable data and clock recovery, and a transmitter which accepts either single or dual-rail digital inputs for signal transmission to the line using a low output impedance line driver. The device also includes a crystal-less jitter attenuator which, depending on system requirements, can be selected in the receive or transmit path through the Host or Hardware Mode control. XRT82L24A is a low power CMOS device operating on a single 3.3V supply with 5V tolerant digital inputs. FEATURES * Fully integrated quad, short-haul PCM transceivers for E1 applications. * On Chip Receive Equalizer and Transmit Pulse Shaper for CEPT 75 and 120 line terminations * On chip clock recovery circuit * Transformer or capacitor coupled receiver inputs * Crystal-less jitter attenuator can be selected in the transmit or receive path * High receiver interference immunity
* Per-channel transmit power shutdown * Tri-state transmit output capability * On chip per-channel driver failure monitoring circuit * On chip HDB3/B8ZS/AMI encoder/decoder functions * Supports Gapped Clock for Multiplexer Mapper Applications * Transmit return loss meets or exceeds ETSI 300 166 standard * Meets or exceeds specifications in ITU G.703, G.775, G.736 and G.823; ETSI 300-166 * Meets or exceeds G.783 and G.823 Jitter Specifications * 3.3V or 5.0V Logic level inputs * Single +3.3V Supply Operation * New Patent# 6,313,671B1 Low Power IC I/O Buffer APPLICATIONS * Digital cross connects (DSX-1) * Channel Banks * High speed data transmission line cards * E1 Multiplexer * Public switching systems and PBX interfaces
FIGURE 1. BLOCK DIAGRAM OF THE XRT82L24A E1 LIU (HOST MODE)
Driver Monitor
TVDD_n
TxClk_n/RZData_n TxPOS_n/TDATA_n TxNEG_n
HDB3 Encoder
MUX
Tx/Rx Jitter Attenuator
Tx Timing Control
Tx Pulse Shaper
Line Driver
TTIP_n TRing_n
Enable/ Disable
Remote LoopBack Digital LoopBack Clock Generator
Local Analog LoopBack
TGND_n
MClk
Peak Detector & Slicer Rx Equalizer
RxClk_n RxPOS_n/RDATA_n RxNEG_n/LCV_n
HDB3 Decoder
MUX
Tx/Rx Jitter Attenuator
Timing & Data Recovery
RTIP_n RRing_n
RxLOS_n
Channel 0 Channel 1 Channel 2 Channel 3
LOS Detect
INT RDY_DTACK PClk/Codes PTS1/ClkE PTS2/SR_DR Reset ICT
P Controller & Hardware Interface
Test
ADD [0:3] D[0:7] WR_R/W/TxOFF_0 ALE_AS/TxOFF_2 CS/TxOFF_3 RD_DS/TxOFF_1 HW/HOST
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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FIGURE 2. BLOCK DIAGRAM OF THE XRT82L24A T1/E1/J LIU (HARDWARE MODE)
One of four channels
Driver Monitor Tx/Rx Jitter Attenuator Tx Timing Control Tx Pulse Shaper Line Driver
TVDD_n
TxClk_n/RZData TxPOS _n/TDATA_n TxNEG_n
HDB3 Encoder
MUX
TTIP_n TRing_n
Enable/ Disable
Remote LoopBack Digital LoopBack Clock Generator
Local Analog LoopBack
TGND_n
MClk
Peak Detector & Slicer Rx Equalizer
RxClk_n RxPOS_n/RDATA_n RxNEG_n/LCV_n RxLOS_n
HDB3 Decoder
MUX
Tx/Rx Jitter Attenuator
Timing & Data Recovery
RTIP_n RRing_n
LOS Detect
INT RDY_DTACK PClk/Codes PTS1/ClkE PTS2/SR/DR Reset WR_R/W/TxOFF0 ALE_AS/TxOFF2 CS/TxOFF3 RD_DS/TxOFF1 HW/HOST ICT
Test
P Controler & Hardware Interface
ADD[0] ADD[1] ADD[2] ADD[3]/RxMute D[0]/FIFOS D[1]/LOOPEN_0 D[2]/LOOPEN_1 D[3]/LOOPEN_2 D[4]LOOPEN_3 D[5]/LOOPSEL D[6]/RxJA D[7]TxJA
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
ORDERING INFORMATION
PART NUMBER XRT82L24AIV PACKAGE 100 Lead TQFP (14 x 14 x 1.4mm) OPERATING TEMPERATURE RANGE -40C to +85C
FIGURE 3. PIN OUT OF THE XRT82L24A
100
RxClk_0/RZData_0 RxLOS_0 TxNEG_0 TxPOS_0/TData_0 TxClk_0 Reset PTS1/ClkE PTS2/SR/DR HW/HOST PClk/Codes AGND AVDD DGND WR_R/W/TxOFF_0 RD_DS/TxOFF_1 ALE_AS/TxOFF_2 CS/TxOFF_3 RDY_DTACK INT ICT TxClk_1 TxPOS_1/TData_1 TxNEG_1 RxLOS_1 RxClk_1/RZData_1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
76 75
RxPOS_0/RData_0 RxNEG_0/LCV_0 DVDD DGND AGND RRing_0 RTIP_0 AVDD TGND_0 TRing_0 TVDD_0 TTIP_0 VDD TTIP_3 TVDD_3 TRing_3 TGND_3 AVDD RTIP_3 RRing_3 AGND DGND DVDD RxNEG_3/LCV_3 RxPOS_3/RData_3
100 Lead TQFP
51 50
RxClk_3/RZData_3 RxLOS_3 TxNEG_3 TxPOS_3/TData_3 TxClk_3 A[0] A[1] A[2] A[3]/RxMute MClk GND VDD D[0]/FIFOS D[1]/LoopEN_0 D[2]/LoopEN_1 D[3]/LoopEN_2 D[4]/LoopEN_3 D[5]/LoopSEL D[6]/RxJA D[7]/TxJA TxClk_2 TxPOS_2/TData_2 TxNEG_2 RxLOS_2 RxClk_2/RZData_2
RxPOS_1/RxData_1 RxNEG_1/LCV_1 DVDD DGND DGND RRing_1 RTIP_1 DVDD TGND_1 TRing_1 TVDD_1 TTIP_1 AGND TTIP_2 TVDD_2 TRing_2 TGND_2 AVDD RTIP_2 RRing_2 AGND DGND(PLL) DVDD(PLL) RXNEG_2/LCV_2 RXPOS_2/RData_2
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... APPLICATIONS .............................................................................................................................................. Figure 1. Block Diagram of the XRT82L24A E1 LIU (Host Mode) ......................................................... Figure 2. Block Diagram of the XRT82L24A T1/E1/J LIU (Hardware Mode) ........................................ Figure 3. Pin Out of the XRT82L24A ....................................................................................................... 1 1 1 2 3
TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTION ............................................................................................................. 4
RECEIVER SECTIONS .................................................................................................................................... TRANSMITTER SECTIONS .............................................................................................................................. MICROPROCESSOR INTERFACE ...................................................................................................................... CLOCKS ....................................................................................................................................................... JITTER ATTENUATOR .................................................................................................................................... CONTROL ..................................................................................................................................................... POWER SUPPLIES AND GROUNDS ................................................................................................................. 4 4 5 7 7 7 8
SYSTEM-FUNCTIONAL DESCRIPTION ......................................................................... 10
RECEIVER .................................................................................................................................................. 10 JITTER ATTENUATOR .................................................................................................................................. 10 GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................. 10 TABLE 1: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ............................................... 10 HDB3/AMI DECODER ................................................................................................................................. 10 RECEIVER LOSS OF SIGNAL (LOS) .............................................................................................................. 10 CONDITIONS FOR DECLARING AND CLEARING LOS IN THE E1 MODE. ............................................................ 11 RECEIVE DATA MUTING .............................................................................................................................. 11 LOOP-BACK MODES .............................................................................................................................. 11 REMOTE LOOP-BACK (RLOOP) MODE ...................................................................................................... 11 DIGITAL LOCAL LOOP-BACK (DLOOP) MODE ............................................................................................... 11 ANALOG LOCAL LOOP-BACK (ALOOP) MODE .............................................................................................. 12 Figure 4. Remote Loop-Back with jitter attenuator selected in receive path .................................... 12 Figure 5. Remote Loop-Back with jitter attenuator selected in transmit path .................................. 12 Figure 6. Digital Local Loop-Back with option to transmit all "ones" to the line (JA selected & in receive path) .............................................................................................................................. 13 Figure 7. Digital Local Loop-Back with option to transmit all "ones" to the line (JA selected & in transmit path) ......................................................................................................................... 13 Figure 8. Analog Local Loop-Back signal flow Jitter Attenuator selected & in Receive path ........ 14 Figure 9. Analog Local Loop-Back signal flow Jitter Attenuator selected & in transmit path ........ 14 RESET OPERATION ..................................................................................................................................... 14 RECEIVER MODES OF OPERATION ............................................................................................................... 14 RECEIVE DATA INVERT MODE ..................................................................................................................... 14 Figure 10. Data changes on rising edge of Clk and Data is sampled on falling edge ..................... 15 Figure 11. Data changes on falling edge of Clk and is sampled on rising edge .............................. 15 TRANSMIT CLOCK SAMPLING EDGE ............................................................................................................. 15 SINGLE RAIL, DUAL RAIL .............................................................................................................................. 15 TRANSMIT ALL ONES (TAOS) ..................................................................................................................... 15 HDB3/AMI ENCODER ................................................................................................................................. 15 TRANSMIT PULSE SHAPER .......................................................................................................................... 16 DRIVER MONITOR ....................................................................................................................................... 16 TRANSMIT OFF CONTROL ............................................................................................................................ 16 INTERFACING THE XRT 82L24A TO THE LINE .............................................................................................. 16 Figure 12. XRT 82L24A Channel 1in an E1 unbalanced 75 W application ........................................ 16 Figure 13. XRT 82L24A Channel 1 - E1 120 W balanced application ................................................. 17 TABLE 2: E1 RECEIVER ELECTRICAL CHARACTERISTICS ............................................................................. 18
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 3: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ....................................................................... TABLE 4: TRANSMIT PULSE MASK SPECIFICATION ...................................................................................... Figure 14. ITU G.703 E1 Pulse Template .............................................................................................. TABLE 5: DC ELECTRICAL CHARACTERISTICS ............................................................................................ TABLE 6: POWER CONSUMPTION (TA=-40C TO 85C, VDD=3.3V + 5%, UNLESS OTHERWISE SPECIFIED.) .. TABLE 7: AC ELECTRICAL CHARACTERISTICS ............................................................................................ Figure 15. Transmit Clock and Input Data Timing .............................................................................. Figure 16. Receive Clock and Output Data Timing. ............................................................................ TABLE 8: MICROPROCESSOR INTERFACE SIGNAL ........................................................................................ TABLE 9: MICROPROCESSOR REGISTER MAP ............................................................................................. TABLE 10: COMMAND CONTROL REGISTER 0 ............................................................................................. TABLE 11: COMMAND CONTROL REGISTER 1 ............................................................................................. TABLE 12: CHANNEL STATUS REGISTER .................................................................................................... TABLE 13: CHANNEL MASK REGISTER ....................................................................................................... TABLE 14: CHANNEL CONTROL REGISTER ................................................................................................ Figure 17. Intel Interface Timing (Read) ............................................................................................... Figure 18. Intel Interface Timing (Write) ............................................................................................... TABLE 15: INTEL INTERFACE TIMING SPECIFICATIONS ................................................................................. Figure 19. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ... Figure 20. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ... Figure 21. Microprocessor Interface Timing - Reset Pulse Width ..................................................... TABLE 16: MOTOROLA INTERFACE TIMING SPECIFICATION .......................................................................... JITTER TOLERANCE .................................................................................................................................... Figure 22. Receive Maximum Jitter Tolerance .................................................................................... Figure 23. Receiver Jitter Transfer Function (Jitter Attenuator disabled) ........................................ Figure 24. Jitter Attenuation Function ................................................................................................. ORDERING INFORMATION ............................................................................................................................ PACKAGE DIMENSIONS 100 LEAD TQFP 14X14MM ..................................................................................... REVISION HISTORY .....................................................................................................................................
19 19 20 20 21 21 22 22 23 24 25 26 27 28 29 30 30 31 32 32 33 33 34 34 35 35 36 36 37
ABSOLUTE MAXIMUM RATINGS ................................................................................... 21
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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PIN DESCRIPTION
PIN DESCRIPTIONS
PIN # NAME TYPE DESCRIPTION
RECEIVER SECTIONS
1 25 51 75 2 24 52 74 100 26 50 76 99 27 49 77 RxCLK_0/RZData_0 RxCLK_1/RZData_1 RxCLK_2/RZData_2 RxCLK_3/RZData_3 RxLOS_0 RxLOS_1 RxLOS_2 RxLOS_3 RxPOS_0/RData_0 RxPOS_1/RData_1 RxPOS_2/RData_2 RxPOS_3/RData_3 RxNEG_0/LCV_0 RxNEG_1/LCV_1 RxNEG_2/LCV_2 RxNEG_3/LCV_3 O Receiver_n Clock Output Rzdata Output: In Data Slicer Mode, (register 0, bit 7 = 1) or in Hardware Mode when MClk is absent, this signal is OR-ed RZdata after the slicers. Receiver_n Loss of Signal. This signal is asserted "High" to indicate loss of signal at the receive input.
O
O
Receiver 1 Positive Data Output: In dual-rail mode, this signal is the receive P-rail output data. Receiver 1 NRZ Data Output: In single-rail mode, this signal is the receive output data. Receiver_n Negative Data Output: In dual-rail mode, n-rail data are sent to the framer. Line Code Violation Output - Channel_n: In single-rail mode, this signal output "High" for one receive clock cycle to indicate a code violation is detected in the received data. If AMI coding is selected, every bipolar violation received will cause this pin to go "High". Receiver_n Differential Negative Input.
O
95 31 45 81 94 32 44 82 67
RRing_0 RRing_1 RRing_2 RRing_3 RTIP_0 RTIP_1 RTIP_2 RTIP_3 RXMUTE
I
I
Receiver_n Differential Positive Input.
I
Hardware Mode, Receive Muting: Connect this pin "High" to mute RxPOS/RxNEG output to a low state upon receive LOS condition to prevent data chattering. Connect Low to disable muting function.
TRANSMITTER SECTIONS
3 23 53 73 4 22 54 72 TxNEG_0 TxNEG_1 TxNEG_2 TxNEG_3 TxPOS_0/TData_0 TxPOS_1/TData_1 TxPOS_2/TData_2 TxPOS_3/TData_3 I Transmitter_n Negative NRZ Data Input. In dual-rail mode, this signal is the nrail input data for transmitter 0. In single-rail mode, this pin can be left unconnected. Transmitter_n Positive Data Input. In dual-rail mode, this signal is the p-rail input data for transmitter 0. Transmitter 0 Data Input. In single-rail mode, this pin is used as the NRZ input data for transmitter 0.
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
PIN DESCRIPTIONS
PIN # 5 21 55 71 NAME TxClk_0 TxClk_1 TxClk_2 TxClk_3 TYPE I DESCRIPTION Transmitter_n Clock Input: E1 rate at 2.048MHz 50ppm. During normal operation both in Host Mode and Hardware Mode, TxClk is used for sampling input data at TxPOS/TData and TxNEG, while MCLK is used as the timing reference for the transmit pulse shaping circuit. If TxClk is active while MClk is not present, TxPOS and TxNEG accepts NRZ data input and the transmit pulse width is determined by TxClk clock duty cycle. If TxClk is tied to "Low", TxPOS and TxNEG input accepts RZ data format and the pulse width is determined by the duty cycle of the input data. In RZ Mode, single-rail data format is not supported. In Hardware Mode, if TxClk is tied "High" for more than 10 s, then TAOS (a continuous all one's AMI signal) will be transmitted to the line using MCLK as timing reference. If TxClk_0 is tied "Low" for more than 10 s, the transmitter will be powered down and the output will be tri-stated. Powered-down Transmitter_n: In Hardware Mode, tie this pin "High" to power-down channel 0 transmitter and set TTIP_n and TRing_n to high impedance. NOTE: Internally pulled -up with a 50k resistor. Transmitter_n Ring Output: Negative Differential data output to the line.
14 15 16 17 91 35 41 85 89 37 39 87
TxOFF_0 TxOFF_1 TxOFF_2 TxOFF_3 TRing_0 TRing_1 TRing_2 TRing_3 TTIP_0 TTIP_1 TTIP_2 TTIP_3
I
O
O
Transmitter_n Tip Output: Positive Differential data output to the line.
MICROPROCESSOR INTERFACE
6 RESET I Hardware Reset (Active Low). When this pin is tied Low for more than 10S, the device is put in the reset state. NOTE: Internally pulled -up with a 50k resistor. Processor Type Select bit 1: Host Mode In Host Mode the appropriate bits are set in the command mode
PTS1 0 1 0 1 PTS2 0 0 1 1 8HC11,8081,80C188 (async.) Motorola 68K (async.) Intel x86 (sync.) Intel i906,Motorola 860 (sync.)
7
PTS1
I
ClkE
I
Hardware Mode: The state of the ClkE input controls the sampling edge of both TxClk and RxClk. A "1" selects the positive edge of TxClk and RxClk A "0" selects the negative edge of TxClk and RxClk.
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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PIN DESCRIPTIONS
PIN # 8 NAME PTS2 TYPE I DESCRIPTION Host Mode: Processor Type Select Input bit 2: See description for pin 7. Hardware Mode Single rail/Dual Rail Control Connect this pin "Low" to select transmit and receive data format in dual-rail mode. In this mode, HDB3 encoder and decoder are not available. Connect this pin "High" to select single-rail data format. NOTE: Internally pulled -downwith a 50k resistor.
SR/DR
9
HW/HOST
I
Mode Control Input:
This pin is used to select the operating mode of the device, (Hardware Mode or Host Mode.) In Hardware Mode, the parallel Microprocessor interface is disabled and enables all hardware control pin functions. In Host Mode, the parallel microprocessor interface pins are used for control functions. Pin 9 "Low" "High" Operating Mode Host Mode Hardware Mode
NOTE: Internally pulled "High" with 50k.
10 PCLK I Processor Clock Input. Input clock for synchronous microprocessor operation. Maximum clock rate is 16 MHz. This pin is internally pulled-up for asynchronous microprocessor interface when no clock is present. Coding/Decoding Select. In Hardware Mode, if single-rail data format is selected (pin 8 ="1"), connect this pin "High" to select AMI encoding and decoding. Connect this pin Low to select HDB3. Write Input (Read/Write). With Intel bus timing, a Low pulse on WR selects a write operation when CS pin is Low. When configured in Motorola bus timing, a "High" pulse on R/W selects a read operation and a Low pulse on R/W selects a write operation when CS is Low. Read Input (Data Strobe). With Intel bus timing, a Low pulse on RD selects a read operation when CS pin is Low. When configured in Motorola bus timing, a Low pulse on DS indicates a read or write operation when CS pin is Low. Address Latch Input (Address Strobe). With Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE. When configured in Motorola bus timing, the address inputs are latched into the internal register on the falling edge of AS. Chip Select Input. This signal must be Low in order to access the parallel port.
I Codes
14
WR_R/W
I
15
RD_DS
I
16
ALE_AS
I
17
CS
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
PIN DESCRIPTIONS
PIN # 18 NAME RDY_DTACK TYPE O DESCRIPTION Ready Output (Data Transfer Acknowledge Output). With Intel bus timing, RDY is asserted "High" to indicate the device has completed a read or write operation. When configured in Motorola bus timing, DTACK is asserted Low to indicate the device has completed a read or write cycle. Host Mode, Microprocessor Interface Address Bus [3] Host Mode, Microprocessor Interface Address Bus [2] Host Mode, Microprocessor Interface Address Bus [1] Host Mode, Microprocessor Interface Address Bus [0]. Data Bus[7:0]. Microprocessor read/write data bus pins.
67 68 69 70 56 57 58 59 60 61 62 63
A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
I
I/O
CLOCKS
66 MCLK I Master Clock Input. This signal is an independent 2.048MHz clock with accuracy better than 50ppm and duty cycle within 40% to 60%. The function of MCLK is to provide internal timing for the PLL clock recovery circuit, jitter attenuator block, reference clock during transmit all ones data and timing reference for the microprocessor in Host Mode operation. If MClk is absent, all receive channels perform as analog front-end (AFE). The OR-ed RZ data is also available at RxClk output in this mode, instead. The clock recovery function is disabled.
JITTER ATTENUATOR
56 TXJA I Transmit Jitter Attenuator Select. In Hardware Mode, connect this pin "High" to select jitter attenuator in the transmit path and connect Low to disable jitter attenuator. Setting RXJA simultaneously "High" also disables jitter attenuator selection. Receive Jitter Attenuator Select. In Hardware Mode, connect this pin "High" to select jitter attenuator in the receive path and connect Low to disable jitter attenuator. Setting TXJA simultaneously "High" also disables jitter attenuator selection.
57
RXJA
I
CONTROL
8 SR/DR I Single rail/Dual Rail Control: Hardware Mode Connect this pin "Low" to select transmit and receive data format in dual-rail mode. In this mode, HDB3 encoder and decoder are not available. Connect this pin "High" to select single-rail data format. NOTE: Internally pulled -down with a 50k resistor. Coding/Decoding Select. In Hardware Mode, if single-rail data format is selected (pin 8 ="1"), connect this pin "High" to select AMI encoding and decoding. Connect this pin Low to select HDB3.
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Codes
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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PIN DESCRIPTIONS
PIN # 19 NAME INT TYPE O DESCRIPTION Interrupt Output. This pin is asserted Low to indicate an alarm condition has occurred within the device. Interrupt generation can be globally disabled by setting the GIE bit to a "0" in the command control register. NOTE: This pin is an open drain output and requires an external 10K pull-up resistor. In-Circuit Testing (Active Low). When this pin is tied Low, all output pins are forced to high impedance state for in-circuit testing. NOTE: Internally pulled -up with 50k. DLoop-back Mode Select. In Hardware Mode, if LOOPEN_(0-3) is "High", this pin is used for selecting loop-back mode. Connect this pin "High" to select local loop-back and Low to select remote loop-back. Digital Loop-back is not supported in Hardware Mode. Loop-back Enable - Channel_n: In Hardware Mode: Connect this pin "High" to enable channel_n loop-back operation. Remote or local loop-back is determined by pin 58 setting. FIFO Size Select. In Hardware Mode, connect this pin "High" selects 64 bit FIFO depth and connect Low to select 32 bit FIFO depth.
20
ICT
I
58
LOOPSEL
I
62 61 60 59 63
LOOPEN_0 LOOPEN_1 LOOPEN_2 LOOPEN_3 FIFOS
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I
POWER SUPPLIES AND GROUNDS
12 28 33 90 36 40 86 43 48 64 78 11 13 29 30 92 34 42 84 AVDD DVDD DVDD TVDD_0 TVDD_1 TVDD_2 TVDD_3 AVDD DVDD DVDD DVDD AGND DGND DGND DGND TGND_0 TGND_1 TGND_2 TGND_3 **** **** **** **** Analog Positive Supply(3.3V 5%) Digital Positive Supply(3.3V 5%) Digital Positive Supply(3.3V 5%) Transmitter_n Analog Positive Supply(3.3V 5%).
**** **** **** **** **** **** **** **** ****
Analog Positive Supply(3.3V 5%) Digital Positive Supply(3.3V 5%) Digital Positive Supply(3.3V 5%) Digital Positive Supply(3.3V 5%) Analog Ground Digital Ground Digital Ground Digital Ground Transmitter_n Analog Ground.
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
PIN DESCRIPTIONS
PIN # 38 46 47 65 79 80 83 88 93 96 97 98 NAME AGND AGND DGND DGND DGND AGND AVDD AVDD AVDD AGND DGND DVDD TYPE **** **** **** **** **** **** **** **** **** **** **** **** Analog Ground Analog Ground Digital Ground Digital Ground Digital Ground Analog Ground Analog Positive Supply(3.3V 5%) Analog Positive Supply(3.3V 5%) Analog Positive Supply(3.3V 5%) Analog Ground Digital Ground Digital Positive Supply(3.3V 5%) DESCRIPTION
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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SYSTEM-FUNCTIONAL DESCRIPTION
A simplified single channel block diagram of the XRT 82L24A is presented in Figure 1. The XRT 82L24A consists of four identical transmit and receive channels for E1(2.048 Mbps) PCM systems. The operational mode of each channel of the line interface can be configured by the microprocessor interface (Host Mode) or by Hardware control. RECEIVER At the receiver input, cable attenuated AMI signals can be coupled to the receiver using a capacitor or a 1:2 transformer. The receive signal first goes through the equalizer for signal conditioning before being applied to the data recovery circuit. The data recovery circuit includes a peak detector which is set typically at 50% for E1 of the equalizer output peak amplitude for data slicing. After the data slicers, the digital representation of the AMI signals goes to the clock recovery circuit for timing recovery and subsequently to the HDB3 decoder (if selected) before they are output via the RxPOS/RDATA and RxNEG/LCV pins. The digital data output can be in dual-rail or single-rail mode depending on the option selected. Clock and timing recovery is accomplished by means of a digital PLL scheme which can tolerate high input jitter and meets or exceeds the jitter tolerance requirements as specified in the ITU - G.823 standard. JITTER ATTENUATOR To reduce jitter in the transmit line signal or recovered clock and data signals, a crystal-less jitter attenuator with a 32x2 bit or 64x2 bit FIFO is provided for each channel. The jitter attenuator can be configured to op-
erate in either the transmit or receive path, or it can be disabled through Host or Hardware Mode control. The jitter attenuator design is based on a digital scheme that uses the MCLK signal as a reference input. No other high frequency clock is necessary. With the jitter attenuator selected, the typical throughput delay is 16 bits for a 32 bit FIFO depth or 32 bit for a 64 bit FIFO depth. The design of the jitter attenuator is such that if the write and read pointers of the FIFO are within two bits of overflowing or underflowing, the bandwidth of the jitter attenuator is automatically widened in order to permit the "Jitter Attenuator" PLL to track the short term input jitter to avoid data corruption. When this situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside the two bit window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth requirement as specified in ITU- G.736 and ITU- I.431standards.
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)
The XRT82L24A LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the 32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap width of the XRT82L24A is shown in Table 1.
TABLE 1: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH 32-Bit 64-Bit MAXIMUM GAP WIDTH 20 UI 50 UI
NOTE: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.
HDB3/AMI DECODER The decoder function is only active if the chip has been configured to operate in the single-rail mode. When the single-rail mode is selected, the receive line signal will be decoded according to HDB3 rules for E1. Further, any bipolar violation of the HDB3 line coding scheme will be flagged as a Line Code Violation via the LCV output pin. The LCV output pin will be pulsed high for one RxClk cycle for each line code violation that is detected. Excessive number of zeros in the receive data stream are also flagged as a line 10
code violation via the same output pin. If AMI decoding is selected in single-rail mode operation, every bipolar violation in the receive data stream is reported as error at the LCV pin. RECEIVER LOSS OF SIGNAL (LOS) The receiver loss of signal monitoring function is implemented using both analog and digital detection schemes compatible with ITU G.775 requirements. When the amplitude of the E1line signal at RTIP/ RRING drops 16dB (typical) below the 0dB nominal level the digital circuit is activated to parse through and check for 32 consecutive zeros before LOS is asserted, to indicate loss of input signal. The number of
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
consecutive zeros before LOS is declared can be increased to 4096 bits. During extended LOS Mode, the LOS condition will be cleared when 4096 more valid data bits are present (when operating in the Host Mode). The LOS condition is cleared when the input signal rises above 16dB below 0dB nominal level and meets 12.5% density of 4 ones in a 32 bit window with no more than 16 consecutive zeros. Clock signals generated when LOS is declared The output signal at the RxClk output pin depends upon the type of LOS condition that is occurring. Complete Loss of Signal (Zero Amplitude) If the XRT 82L24A experiences a complete Loss of Signal (e.g., no signal amplitude), then the XRT 82L24A Clock Recovery PLL enters the Training Mode, and Differentially begins to lock onto the signal applied to the MCLK input pin. As a consequence, the Clock Recovery PLL will begin to drive a clock signal to the Terminal Equipment (via the RxClk output pin), which is derived from the MCLK input pin. Degraded Type of Loss of Signal Event (Non-Zero Amplitude) If the XRT 82L24A experiences a degraded type of LOS event (e.g., where there is still a small amount of discernible signal amplitude in the line signal, but small enough to qualify as an LOS event) then the Clock Recovery PLL could lock onto this degraded line signal and will subsequently drive the same frequency via the RxClk output pins. CONDITIONS FOR DECLARING AND CLEARING LOS IN THE E1 MODE. Each E1 channel of the XRT 82L24A has two criteria for LOS Detection, Analog and Digital. A channel will declare a LOS condition when both of these LOS Detectors detect an LOS condition. Analog LOS Detector The Analog LOS Detector will declare an LOS condition, if it determines that the amplitude of the incoming line signal has dropped to less than -15dB (below the nominal pulse amplitude of 3V for twisted-pair, or 2.37V for coaxial-cable) for at least 32 bit-periods. The Analog LOS Detector will clear the LOS condition, if it determines that the incoming line signal is no more than 12.5dB below the nominal 3V pulse amplitude.
NOTE: The difference in the signal level required to declare and clear LOS is 2.5dB. This 2.5dB hysteresis is designed into the Analog LOS Detector circuitry, in order to prevent chattering in the LOS output pin or bit-field.
The Digital LOS Detector will declare an LOS condition, if it detects a string of at least 32 consecutive "0"s. The Digital LOS Detector will clear the LOS condition, if it determines that the incoming E1 line signal has a pulse density of 12.5% or more without 16 consecutive "0's" for at least 32 consecutive bit periods.
NOTE: The pulse density requirement of 12.5% accounts for HDB3 coding.
RECEIVE DATA MUTING The XRT 82L24A permits the user to "MUTE" the recovered data output signals anytime the LOS condition is declared. If the user invokes this function, then the RPOS/RDAT and RNEG output pins will be pulled to GND for the duration that the LOS condition exists. This feature is useful in that it prevents the LIU from routing electrical noise (which has been "recovered" by the Clock Recovery PLL) to the Framer IC and preventing it from declaring an LOS condition. This feature is enabled by setting the RXMUTE bit to a "1" in the Host Mode (Register 1, Bit 2 Location) or by connecting pin 67 High in the Hardware Mode. LOOP-BACK MODES Each channel within the XRT 82L24A can be configured to operate in any of the following loop-back modes: * Remote Loop-Back Mode * Digital Local Loop-Back Mode * Analog Local Loop-Back Mode Each of these loop-back modes are described in some detail below. REMOTE LOOP-BACK (RLOOP) MODE With Remote Loop-Back activated, (Channel Control Register bit 2 = "1") in Host Mode or in Hardware Mode with LoopSEL (pin 58) tied Low and LoopEN tied High received data after the jitter attenuator (if selected) is looped back to the transmit path using RxClk as transmit timing. In this mode the data/signals applied to the TxClk, TPOS/TDAT and TNEG input pins are ignored, while RxClk and received data will continue to be available at their respective output pins. Simultaneously setting RLOOP and ALOOP active is not allowed (see Loop-Back Mode in Figure 4 & Figure 5). Remote loop-back has priority over TAOS. DIGITAL LOCAL LOOP-BACK (DLOOP) MODE The Digital Local Loop-Back mode allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder/ decoder and the jitter attenuator. In this mode, the receive line signal is ignored, but the transmit data will
Digital LOS Detector 11
XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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be sent to the line uninterrupted. This loop back feature allows users to configure the line interface as a pure jitter attenuator. (see Loop-Back Mode in Figure 6 & Figure 7).
NOTE: Digital Local Loop-Back is not supported in Hardware Mode.
ANALOG LOCAL LOOP-BACK (ALOOP) MODE
With Analog Local Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog input of the receiver. External inputs at RTIP/ RRING in this mode are ignored while valid transmit data continues to be sent to the line. Analog LoopBack exercises most of the functional blocks of the line interface (see Loop-Back Mode in Figure 8 & Figure 9).
FIGURE 4. REMOTE LOOP-BACK WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH
TxPOS TxNEG TxClk
Encoder Timing Control Tx
TTIP TRing
RxClk RxPOS RxNEG
Decoder JA Clock & Data Recovery
RTIP
Rx
RRing
FIGURE 5. REMOTE LOOP-BACK WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
TxPOS TxNEG TxClk
Encoder JA Timing Control Tx
TTIP TRing
RxClk RxPOS RxNEG
Decoder Clock & Data Recovery
RTIP
Rx
RRing
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
FIGURE 6. DIGITAL LOCAL LOOP-BACK WITH OPTION TO TRANSMIT ALL "ONES" TO THE LINE (JA SELECTED & IN
RECEIVE PATH)
TxPOS TxNEG TxClk
Encoder
TAOS
Timing Control Tx
TTIP TRing
RxClk RxPOS RxNEG
Decoder JA Clock & Data Recovery
RTIP
Rx
RRing
FIGURE 7. DIGITAL LOCAL LOOP-BACK WITH OPTION TO TRANSMIT ALL "ONES" TO THE LINE (JA SELECTED & IN
TRANSMIT PATH)
TxPOS TxNEG TxClk TAOS RxClk RxPOS RxNEG
Decoder Clock & Data Recovery Encoder JA Timing Control Tx
TTIP TRing
RTIP
Rx
RRing
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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FIGURE 8. ANALOG LOCAL LOOP-BACK SIGNAL FLOW JITTER ATTENUATOR SELECTED & IN RECEIVE PATH
TxPOS TxNEG TxClk
Encoder Timing Control
TTIP
Tx
TRing
RxClk RxPOS RxNEG
Decoder JA Clock & Data Recovery
RTIP
Rx
RRing
FIGURE 9. ANALOG LOCAL LOOP-BACK SIGNAL FLOW JITTER ATTENUATOR SELECTED & IN TRANSMIT PATH
TxPOS TxNEG TxClk
Encoder JA Timing Control
TTIP
Tx
TRing
RxClk RxPOS RxNEG
Decoder Clock & Data Recovery
RTIP
Rx
RRing
RESET OPERATION The XRT 82L24A provides both Hardware and Software resets. In Hardware reset, with pin 6 forced to "0" for more than 10s, the entire state of the device including the microprocessor R/W registers are reset. In Software reset, only the state of the interface is reset (the microprocessor registers are not affected). RECEIVER MODES OF OPERATION Through the microprocessor interface or in Hardware Mode, XRT 82L24A offers several alternative receive
modes of operation making it flexible for different applications as dictated by the system requirements. RECEIVE DATA INVERT MODE Receive output data by default is active high at RxPOS/RDATA and RxNEG/LCV pins. These signals can be changed to active Low by setting the DATAP bit in the interface register(Register 1, Bit 3 = "1"). In single rail mode DATAP = "1", (Register 0, Bit 7 = "1"), LCV output also becomes active Low. Data invert Mode is only available in Host Mode.
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
FIGURE 10. DATA CHANGES ON RISING EDGE OF CLK AND DATA IS SAMPLED ON FALLING EDGE
Clk
Data
Data Sampled
Data Sampled
FIGURE 11. DATA CHANGES ON FALLING EDGE OF CLK AND IS SAMPLED ON RISING EDGE
Clk
Data Data Sampled Data Sampled
RxClk Clock Sampling Edge The sampling edge of the RxClk output can be changed through control bit RClkE within the interface register for receive output data re-timing. With RClkE="1", (Bit 5 = "1"), data is validated on the rising edge of RxClk and with RClkE="0", (Bit 5 = "0"),, receive data is validated on the falling edge of RxClk. In Hardware Mode, the state of pin 7 (ClkE) controls the rising or falling edge of RxClk for data re-timing. TRANSMIT CLOCK SAMPLING EDGE NRZ Transmit data at TxPOS/TDATA or TxNEG is clocked serially into the device using TxClk. With the interface register bit 4 (TClkE="1"), input data is sampled on the rising edge of TxClk. The sampling edge is inverted when TClkE= "0". In Hardware Mode, the state of pin 7 (ClkE) controls the sampling edge of both TxClk and RxClk. SINGLE RAIL, DUAL RAIL Transmit data format can be in dual-rail (SR/DR=1) or single-rail modes (SR/DR=0). In Hardware Mode, dual or single-rail format is determined by the state of pin 8. For single-rail mode operation, NRZ data can be applied to TxPOS/TDATA with TxClk, while TxNEG input is left unconnected. The transmitter converts NRZ input data into differential signal for trans-
mission to the line using low impedance output drivers. TRANSMIT ALL ONES (TAOS) In the Host Mode, individual channels can be programmed to transmit an all "Ones" AMI signal by setting the per channel bit control TAOS=1. In this mode, input data at TxPOS/TDATA and TxNEG are ignored. In Host Mode, reference clock for TAOS is TxClk. If TxClk is not available, MCLK is used for transmission. In Hardware Mode, if TxClk is not present and High for more than 10s, TAOS is transmitted using MCLK as a reference. Remote Loop-Back has priority over TAOS request. HDB3/AMI ENCODER The encoder is only available in single-rail mode (SR/ DR=1) in Host Mode, or pin 8 set High in Hardware Mode. In an E1 system, if interface register CODES=0, HDB3 encoding is selected. Input data applied to TxPOS/TDATA which contains more than four consecutive zeros will be removed and replaced by "000V" or "B00V", where "B" indicates a pulse conforming with bipolar rule and "V" represents a pulse violating the rule. With register CODES="1", AMI coding is selected. In Hardware Mode, HDB3 or AMI coding selection is determined by the state of pin 10.
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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The choice of these codes is made such that an odd number of "B" pulses is transmitted between consecutive bipolar violation "V" pulses TRANSMIT PULSE SHAPER The transmit pulse shaper uses high a speed clock derived from MCLK to synthesize the shape and width of the transmitted pulse applied to TTIP and TRING. The internal high speed timing generator eliminates the need for a tightly controlled transmit clock TxClk duty cycle. The intrinsic jitter at the transmit output using a jitterfree input clock source and with the jitter attenuator disabled will generate no more than 0.03UIpp. DRIVER MONITOR The driver monitor circuit is used for detecting transmit driver failure by monitoring the activity at TTIP and TRING. Driver failure may be caused by a shortcircuit in the primary of the transformer or system problems at the input. In the Host Mode, when the driver monitor detects no transitions at TTIP and TRING for more than 128 clock cycles, the DMO bit (bit 7) in the interface register is set and results in an interrupt (INT) to be gener-
ated. Driver monitor function is not supported in Hardware Mode. TxPOS/TDATA and TxNEG Polarity In HOST Mode, transmit data at TxPOS/TDATA and TxNEG can be configured for active Low or active High operation, by controlling the state of the DATAP bit in the interface register. Writing a "0" to this bit selects active High data and a "1" selects active Low data. This control bit also selects receive output data polarity (see Receive Data Invert Mode description). This feature is not supported in Hardware Mode. TRANSMIT OFF CONTROL Each transmit channel of the line interface can be shut down by writing a "1" to TxOFF in the channel control interface register. In the "Transmitter off" mode, the entire transmitter is disabled and the outputs at TTIP and TRING are placed in a high impedance state. In Hardware Mode, pins 14 through pin 17 are used for powering down each transmit channel independently. INTERFACING THE XRT 82L24A TO THE LINE The XRT 82L24A in E1 configuration can be transformer coupled to 75 coaxial or 120 twisted pair lines as shown in Figure 12 and Figure 13 below.
FIGURE 12. XRT 82L24A CHANNEL 1IN AN E1 UNBALANCED 75 APPLICATION
TxPO S TxN EG TxLineC lk
4 3 5
TPO S_0 TN EG _0
TTIP_0
89
R1 9.1 1 T1 5 1
BN C C oaxial C able 2
TC lk_0 TR ing_0 91 94
R2 9.1
4 1:2
8 BN C
R xPO S R xN EG R xLineC lk Loss of signal
100 99 1 2
R PO S_0 R N EG _0 R C lk_0 R LO S_0
R TIP_0
5 R3 18.7
T2
1
1
C oaxial C able 2
R R ing_0
95
8 1:2
4
XR T82L24A
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
FIGURE 13. XRT 82L24A CHANNEL 1 - E1 120 BALANCED APPLICATION
TxPO S TxN EG TxLineC lk
4 3 5
TPO S_0 TN EG _0 TC lk_0
TTIP_0
89
R5 9.1 1 T1 5 TTIP Twisted Pair
TR ing_0 R xPO S R xN EG R xLineC lk Loss of signal 100 99 1 2 R PO S_0 R N EG _0 R C lk_0 R LO S_0 R TIP_0
91 94
R6 9.1
4 1:2 5 R4 30.1 T2
8
TR IN G
1
R TIP Twisted Pair
R R ing_0
95
8 1:2
4
R R ing
XR T82L24A
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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TABLE 2: E1 RECEIVER ELECTRICAL CHARACTERISTICS (Vdd=3.3V5%, Ta=-40C to 85C unless otherwise specified)
PARAMETER Receiver loss of signal: Number of consecutive zeros before LOS is set Input signal level at LOS LOS De-asserted Receiver Sensitivity 15 12.5 11 32 20 13 bit dB % ones dB With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. With -18dB interference signal added. With 6dB cable loss Cable attenuation @1024KHz ITU-G.775, ETS1 300 233 MIN TYP. MAX UNIT TEST CONDITIONS
Interference Margin Input Impedance Jitter Tolerance: 20 Hz 700KHz 10KHz---100KHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude
-18 15 10 5 0.3 -
-14
-
dB K
-
-
UIpp
ITU G.823
36
0.5 -
KHz dB Hz
ITU G.736
Jitter Attenuator Corner Frequency(-3dB curve)
Return Loss: 51KHz --- 102KHz 102KHz --- 2048KHz 2048KHz --- 3072KHz
-
10
ITU G.736
14 20 16
-
-
dB dB dB
ITU G.703
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 3: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS (Ta=-40C to 85C, Vdd=3.3V5%, unless otherwise specified)
PARAMETER AMI Output Pulse Amplitude: 75 Application 120 Application Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Output Return Loss: 51KHz --- 102KHz 102KHz --- 2048KHz 2048KHz --- 3072KHz MIN 2.13 2.70 224 0.95 0.95 TYP. 2.37 3.0 244 0.025 MAX 2.60 3.30 264 1.05 1.05 0.05 UNIT V V ns UIpp ITU-G.703 ITU-G.703 TEST CONDITIONS Use transformer with 1:2 ratio and 9.1 resistor in series with each end of primary.
Broad Band with jitter free TxClk applied to the input. ETSI 300 166
8 14 10
-
-
dB dB dB
TABLE 4: TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance Nominal peak voltage of a mark Peak voltage of a space (no mark) Nominal pulse width Ratio of positive and negative pulses imbalance 75 resistive (Coax) 2.37V 0 0.237V 244ns 0.95 to 1.05 120 resistive (Twisted Pair) 3.0V 0 0.3V 244ns 0.95 to 1.05
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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FIGURE 14. ITU G.703 E1 PULSE TEMPLATE
TABLE 5: DC ELECTRICAL CHARACTERISTICS (Vdd=3.3V5%, Ta=25C unless otherwise specified)
PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage @ IOH=-5mA Output Low Voltage @IOL=5mA Input Leakage Current (except Input pins with Pull-up resistor.) Input Capacitance Output Load Capacitance SYMBOL Vdd VIH VIL VOH VOL IL CI CL MIN 3.13 2.0 -0.5 2.4 TYP. 3.3 5.0 MAX 3.46 5.0 0.8 0.4 + 10 25 UNITS V V V V V A pF pF
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 6: POWER CONSUMPTION (TA=-40C TO 85C, VDD=3.3V + 5%, UNLESS OTHERWISE SPECIFIED.)
PARAMETER Power Consumption Power Consumption Power Consumption Power Consumption Power Consumption SYMBOL PC PC PC PC PC MIN. TYP. 450 650 400 540 80 MAX. 650 680 500 600 100 UNITS mW mW mW mW mW CONDITIONS E1(75 Ohm) load. At 50% Mark Density E1(75 Ohm) load. At 100% Mark Density E1(120 Ohm) load. At 50% Mark Density E1(120 Ohm) load. At 100% Mark Density All Transmitters Powered-Down
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Operating Temperature Supply Voltage Theta-JA Theta-JC -65C to + 150C -40C to + 85C -0.5V to + 6.0V 38 C/W 6 C/W
TABLE 7: AC ELECTRICAL CHARACTERISTICS (Vdd=3.3V5%, Ta=25C unless otherwise specified)
PARAMETER E1 MCLK Clock Frequency MCLK Clock Duty Cycle MCLK Clock Tolerance E1 TxClk Clock Period TxClk Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TxClk Rise Time (10%/90%) TxClk Fall Time (90%/10%) RxClk Duty Cycle Receive Data Setup Time Receive Data Hold Time RxClk to Data Delay RxClk Rise Time (10%/90%) with 25pF Loading. RxClk Fall Time(90%/10%) with 25pF Loading Data Pulse Width in Data Slice Mode TCLKP TCDU TSU THO TCLKR TCLKF RCDU RSU RHO RDY RCLKR RCLKF RZData 210 244 SYMBOL MIN 40 30 50 30 45 150 150 TYP 2.048 50 488 50 50 40 40 40 448 MAX 60 70 40 40 55 UNITS MHz % ppm ns % ns ns ns ns % ns ns ns ns ns
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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FIGURE 15. TRANSMIT CLOCK AND INPUT DATA TIMING
TCLKR TCLKP TxCLK TCLKF
TxPOS/TDATA or TxNEG
Data can be active high or active low. TSU THO
Note: Set TCLKE bit-4 "High" in Command Control Register 0 to select TxCLK inversion.
FIGURE 16. RECEIVE CLOCK AND OUTPUT DATA TIMING.
RDY
RCLKR
RCLKF
RxCLK RxPOS or RxNEG RSU Data can be active high or active low. RHO Note: Set RCLKE bit=5 "High"in Command Control Register 0 to select RxCLK inversion.
MICROPROCESSOR INTERFACE XRT 82L24A is equipped with a microprocessor interface for easy device configuration. The parallel port of the XRT 82L24A is compatible with both Intel and Motorola address and data buses.
The device has 4-bit address ADD[3:0] input and 8-bit bi-directional data bus ADD[7:0]. The signals required for a generic microprocessor to access the internal registers are described in Table 8.
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 8: MICROPROCESSOR INTERFACE SIGNAL
D[7:0] ADD[3:0] PTS1 PTS2 Data Input (Output): 8 bits bi-directional data bus for register access. Address Input: 4 bit address to select internal register location. Processor Type Select:
PTS1 0 1 0 1 PTS2 0 0 1 1 8HC11,8081,80C188 (async.) Motorola 68K (async.) Intel x86 (sync.) Intel i906,Motorola 860 (sync.)
PCLK ALE_AS
Process Clock Input: Input clock for synchronous microprocessor operation. Maximum clock speed is 16MHz. This pin is internally pulled up for asynchronous microprocessor operation if no clock is present. Address Latch Input (Address Strobe): With Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE. When configured in Motorola bus timing, the address inputs are latched into the internal register on the falling edge of AS. Chip Select Input: This signal must be low in order to access the parallel port. Read Input (Data Strobe): With Intel bus timing, a low pulse on RD selects a read operation when CS pin is low. When configured in Motorola bus timing, a low pulse on DS indicates a read or write operation when CS pin is low. Write Input (Read/Write): With Intel bus timing, a low pulse on WR selects a write operation when CS pin is low. When configured in Motorola bus timing, a high pulse on R/W selects a read operation and a low pulse on R/W selects a write operation when CS pin is low.
CS RD_DS
WR_R/W
RDY_DTACK Ready Output (Data Transfer Acknowledge Output): With Intel bus timing, RDY is asserted high to indicate the device has completed a read or write operation. When configured in Motorola bus timing, DTACK is asserted low to indicate the device has completed a read or write operation. INT Interrupt Output: This pin is asserted low to indicate an interrupt caused by an alarm condition in the device status registers. The activation of this pin can be blocked by the interrupt status register bit.
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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TABLE 9: MICROPROCESSOR REGISTER MAP
REGISTER NUMBER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Command Control Registers (Read/Write) 0 1 0000 0001 SR/DR Reserved (Set to 0) reset=0 RZData Reserved (Set to 0) reset=0 RCLKE FIFOS reset=0 TCLKE RXJA reset=0 DATAP TXJA reset=0 CODES RXMUTE reset=0 IMASK EXLOS reset=0 SRESET ICT reset=0
Channel 0 Register 2 3 4 0010 0011 0100 DMO0 Reserved Reserved reset=0 LOS0 Reserved Reserved reset=0 LCV0 TCLK0 DMO0IS MDMO0 DLOOP0 reset=0 LOS0IS MLOS0 RLOOP0 reset=0 LVC0IS MLCV0 TAOS0 reset=0 TCKL0IS MTCKL0 TxOFF0 reset=0
Reserved Reserved Reserved ALOOP0 reset=0 reset=0
Channel 1 Register 5 6 7 0101 0110 0111 DMO1 Reserved Reserved reset=0 LOS1 Reserved Reserved reset=0 LCV1 TCLK1 DMO1IS MDMO1 DLOOP1 reset=0 LLOSIS1 MLOS1 RLOOP1 reset=0 LCV1 MLCV1 TAOS1 reset=0 TCKL1IS MTCKL1 TxOFF1 reset=0
Reserved Reserved Reserved ALOOP1 reset=0 reset=0
Channel 2 Register 8 9 10 1000 1001 1010 DMO2 Reserved Reserved reset=0 LOS2 Reserved Reserved reset=0 LVC2 TCLK2 DMO2IS MDMO2 DLOOP2 reset=0 LLOS2IS MLOS2 RLOOP2 reset=0 LCV2 MLCV2 TAOS2 reset=0 TCKL2IS MTCKL2 TxOFF2 reset=0
Reserved Reserved Reserved ALOOP2 reset=0 reset=0
Channel 3 Register 11 12 13 1011 1100 1101 DMO3 Reserved Reserved reset=0 LOS3 Reserved Reserved reset=0 LCV3 TCLK3 DMO3IS MDMO3 DLOOP3 reset=0 LLOS3IS MLOS3 RLOOP3 reset=0 LCV3 MLCV3 TAOS3 reset=0 TCKL3IS MTCKL3 TxOFF3 reset=0
Reserved Reserved Reserved ALOOP3 reset=0 reset=0
NOTE: Address 1110 and 1111 R/W Registers (14 and 15) are Reserved for Exar Testing Purposes
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 10: COMMAND CONTROL REGISTER 0
COMMAND CONTROL REGISTER 0 PARALLEL PORT ADDRESS: 0000 BIT NO. 7 NAME SR/DR FUNCTION Single/Dual Rail: Writing a "1" to this bit selects transmit and receive data format in single-rail mode. In this mode, HDB3/B8ZS/AMI encoder and decoder are available. Writing a "0" selects dual-rail mode. RZ Data: Writing a "1" to this bit selects receive data to pass to the output after the slicers without re-timing. In this mode, PLL clock recovery, jitter attenuator, decoder and remote loop-back functions are disabled. RxClk Clock Edge: Writing a "1" to this bit selects receive output data to be updated on positive edge of RxClk. Writing a "0" to this bit selects the negative edge of RxClk. TxClk Clock Edge: Writing a "1" to this bit selects positive edge of TxClk to sample input data. Write "0" to select negative edge. DATA Polarity: Writing a "0" to this bit selects transmit input and receive output data to be active-high. Write "1" to select active-low. Coding/Decoding Select: This bit is used in conjunction with SR/DR bit 1. If SR/DR is "1", writing a "0" to this bit selects HDB3 coding. Writing a "1" to this bit position selects AMI code. Global Interrupt Enable: Writing a "0" to this bit globally disables interrupt generation caused by any alarm generated within the line interface. Write a "1" to enable interrupt generation. Software Reset: Writing a "1" to this bit longer than 10s initiates a device reset through the microprocessor interface. All internal circuits are placed in the reset state with this bit set to a "1" except the microprocessor register bits. REGISTER TYPE R/W RESET VALUE 0
6
RZData
R/W
0
5
RCLKE
R/W
0
4
TCLKE
R/W
0
3
DATAP
R/W
0
2
CODES
R/W
0
1
GIE
R/W
0
0
SRESET
R/W
0
NOTE: Register Type Abrbreviation: R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
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XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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TABLE 11: COMMAND CONTROL REGISTER 1
COMMAND CONTROL REGISTER 1 PARALLEL PORT ADDRESS: 0001 BIT NO. 7 6 5 NAME --FIFOS FUNCTION Reserved Must be set to "0" for proper operation. Reserved Must be set to "0" for proper operation. FIFO Size Select: Writing a "1" to this bit selects 64 bit FIFO depth. Write "0" to select 32 bit FIFO depth. Receive Jitter Attenuator: Select: Writing a "1" to this bit selects jitter attenuator in the receive path. If bit 3(TxJA) is also set, jitter attenuator is disabled. Transmit Jitter Attenuator Select: Writing a "1" to this bit selects jitter attenuator in the transmit path. If bit 4(RxJA) is also set, jitter attenuator is disabled. Receive Muting: Writing a "1" to this bit mutes receive data output to a low state during LOS condition to prevent data chattering. Extended LOS: Writing a "1" to this bit extends the number of zeros at the input to 4096 bits, (approximately 2mS), before LOS is declared. In-Circuit-Testing: Writing a "1" to this bit causes all output pins to be in high impedance mode for in-circuit testing. The software ICT function is equivalent to connecting pin 20 to ground. REGISTER TYPE R/W R/W R/W RESET VALUE 0 0 0
4
RxJA
R/W
0
3
TxJA
R/W
0
2
RXMUTE
R/W
0
1
EXLOS
R/W
0
0
ICT
R/W
0
NOTE: Register Type Abrbreviation: R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
26
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 12: CHANNEL STATUS REGISTER
CHANNEL STATUS REGISTER PARALLEL PORT ADDRESS CHANNEL 0: 0010 PARALLEL PORT ADDRESS CHANNEL 1: 0101 PARALLEL PORT ADDRESS CHANNEL 2: 1000 PARALLEL PORT ADDRESS CHANNEL 3: 1011 BIT NO. 7 SYMBOL DMOn FUNCTION Driver Monitor Output: This bit is set to a "1" to indicate current DMO is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the DMO bit. Loss of Signal: This bit is set to a "1" to indicate current LOS condition is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the LOS bit. Line Code Violation: This bit is set to a "1" to indicate current LCV condition is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the LCV bit. Transmit Clock Loss: This bit is set to a "1" to indicate current TxClk clock loss is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the TCKL bit. REGISTER TYPE R RESET VALUE 0
6
LOSn
R
0
5
LCVn
R
0
4
TCKLn
R
0
3
DMOnIS Driver Monitor Output: This bit is set to a "1" every time the state of DMO status changes since last read. This bit is cleared by a read operation. LOSnIS Latched- Loss of signal: This bit is set to a "1" every time the state of LOS changes since last read. This bit is cleared by a read operation. LCVnIS Latched- Line Code Violation: This bit is set to a "1" every time the state of LCV changes since last read. This bit is cleared by a read operation.
RUR
0
2
RUR
0
1
RUR
0
0
TCLKnIS Latched-Transmit Clock Loss. This bit is set to a "1" every time the state of TCKL changes since last read. This bit is cleared by a read operation.
RUR
0
NOTE: n = channel number 0 to 3. NOTE: Register Type Abrbreviation: R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
27
XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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TABLE 13: CHANNEL MASK REGISTER
CHANNEL MASK REGISTER PARALLEL PORT ADDRESS CHANNEL 0: 0011 PARALLEL PORT ADDRESS CHANNEL 1: 0110 PARALLEL PORT ADDRESS CHANNEL 2: 1001 PARALLEL PORT ADDRESS CHANNEL 3: 1100 BIT NO. 7 6 5 4 3 NAME ----DMOnIS This bit is Reserved. This bit is Reserved. This bit is Reserved. This bit is Reserved. Driver Monitor Output Interrupt Status: Writing a "1" to this bit enables DMO alarm interrupt generation. Loss of Signal Interrupt Status: Writing a "1" to this bit enables LOS alarm interrupt generation. Line Code Violation Interrupt Status: Writing a "1" to this bit enables LCV interrupt generation. Transmit Clock Loss Interrupt Status: Writing a "1" to this bit enables TxClk clock loss interrupt generation. FUNCTION REGISTER TYPE R/W R/W R/W R/W R/W RESET VALUE 0 0 0 0 0
2
LOSnIS
R/W
0
1 0
LCVnIS TCKLnIS
R/W R/W
0 0
NOTE: n = channel number 0 to 3. NOTE: Register Type Abrbreviation: R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
28
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 14: CHANNEL CONTROL REGISTER
CHANNEL CONTROL REGISTER Parallel Port Address Channel 0: 0100 Parallel Port Address Channel 1: 0111 Parallel Port Address Channel 2: 1010 Parallel Port Address Channel 3: 1101 BIT NO. 7 6 5 4 SYMBOL **** FUNCTION These bits are Reserved. REGISTER TYPE R/W R/W R/W R/W RESET VALUE 0 0 0 0
LLOOPn
Local Loop-Back: Writing a "1" to this bit enables Analog Local Loop-Back. Simultaneously setting RLOOP High is not allowed. Digital Loop-Back: Writing a "1" to this bit enables Digital Loop-Back. Remote Loop-Back: Writing a "1" to this bit enables Remote Loop-back. Simultaneously setting LLOOP High is not allowed. Transmit All Ones: Writing a "1" to this bit enables the All Ones AMI signal to be transmitted to the line. Transmitter Off: Writing a "1" to this bit powers down the transmitter and places the corresponding output driver in a high impedance mode.
3 2
DLOOPn RLOOPn
R/W R/W
0 0
1
TAOSn
R/W
0
0
TxOFFn
R/W
0
NOTE: n = channel number 0 to 3. NOTE: Register Type Abrbreviation: R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
29
XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
ac
Microprocessor Interface I/0 Timing Intel Interface Timing The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD), Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses FIGURE 17. INTEL INTERFACE TIMING (READ)
minimum external glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency, and with the timings of x86 or I960 family or microprocessors. The interface timing shown in Figure 17 and Figure 18 is described in Table 15.
t64 t65 ALE_AS A[8:0] CS D[7:0] RD_DS WR_R/W RDY_DTCK t70 t69 Address of Target Register t67 Not Valid t66 Valid t68
t701
FIGURE 18. INTEL INTERFACE TIMING (WRITE)
t64 ALE_AS A[8:0] CS D[7:0] RD_DS t66 WR_R/W t770 t65
Address of Target Register t71 Data to be Written t72
t73
30
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 15: INTEL INTERFACE TIMING SPECIFICATIONS
SYMBOL t64 t65 PARAMETER A8 - A0 Setup Time to ALE_AS Low A8 - A0 Hold Time from ALE_AS Low. MIN 4 2 TYP MAX CONDITION ns ns
Intel Type Read Operation
t66 t67 t68 t69 t701 t76 RDS_DS Pulse Width Data Valid from RDS_DS* Low. Data Bus Floating from RDS_DS* High ALE to RD Time RD Time to "NOT READY" (e.g., RDY_DTCK toggling "Low") Minimum Time between Read Burst Access (e.g., the rising edge of RD to falling edge of RD) 60 260 240 2 4 145 ns ns ns ns ns ns
Intel Type Write Operations
t71 t72 t73 t74 t77 Data Setup Time to WR_R/W High Data Hold Time from WR_R/W High High Time between Reads and/ or Writes ALE to WR Time Min Time between Write Burst Access (e.g., the rising edge of WR to the falling edge of WR) CS Assertion to falling edge of WR_R/W 160 0 60 4 60 ns ns ns ns ns
t770
20
ns
31
XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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Motorola Interface Timing The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS), Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing of a Motorola 68000 microprocessor
family with up to 16.67 MHz clock frequency. The interface timing is shown in Figure 19, Figure 20 and Figure 21. The I/O specifications are shown in Table 16.
FIGURE 19. MICROPROCESSOR INTERFACE TIMING - MOTOROLA TYPE PROGRAMMED I/O READ OPERATION
t78
ALE_AS A[8:0] CS D[7:0] RD_DS WR_RW RDY_DTCK Not Valid Valid Data Address of Target Register
t79 t80
FIGURE 20. MICROPROCESSOR INTERFACE TIMING - MOTOROLA TYPE PROGRAMMED I/O WRITE OPERATION
t78
ALE_AS A[8:0] CS D[7:0] RD_DS WR_RW RDY_DTCK t82 Address of Target Register t81
Data to be Written
32
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.
XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
FIGURE 21. MICROPROCESSOR INTERFACE TIMING - RESET PULSE WIDTH
t90 Reset
TABLE 16: MOTOROLA INTERFACE TIMING SPECIFICATION
SYMBOL PARAMETER MIN TYP MAX UNITS
Microprocessor Interface - Motorola Read Operations (see Figure 19) t78 t79 t80 A3 - A0 Setup Time to falling edge of ALE_AS Rising edge of RD_DS to rising edge of RDY_DTCK delay Rising edge of RDY_DTCK to tri-state of D[7:0] 5 0 0 ns ns ns
Microprocessor Interface - Motorola Write Operations (see Figure 20) t78 t81 t82 A3 - A0 Setup Time to falling edge of ALE_AS D[7:0] Setup Time to falling edge of RD_DS Rising edge of RD_DS to rising edge of RDY_DTCK delay 5 10 0 ns ns ns
Reset pulse width - both Motorola and Intel Operations (see Figure 21) t90 Reset pulse width 30 ns
33
XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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JITTER TOLERANCE Input Jitter Tolerance Measurements are presented for the following two situations. 1. The Jitter Attenuator within the Channel-UnderTest is disabled. 2. The Jitter Attenuator within the Channel-UnderTest is enabled and configured to operate in the Receive Path. FIGURE 22. RECEIVE MAXIMUM JITTER TOLERANCE
10 1000
3
The results of the Input Jitter Tolerance Measurements are plotted in Figure 22. Test Conditions * Test Pattern 2^15-1 * (-6dB) Cable Loss
JAT D isabled
10 100
2
JAT 64bits JAT 32bits
Input Jitter (UIp-p)
10 10
1
IT U -T G .823 M ask
1 10
0
.1 10
-1
10
0
10
1
10
2
10 (Freq.(MHz))
3
10
4
10
5
34
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
Receiver Jitter Transfer Function (Jitter Attenuator disabled)
Test Conditions: * Test Pattern 2^15-1 - Input Jitter 0.5UIp-pThe results of the Input Jitter Tolerance Measurements with the Jitter Attenuator enabled and configured to operate in the receive path are plotted in Figure 23.
FIGURE 23. RECEIVER JITTER TRANSFER FUNCTION (JITTER ATTENUATOR DISABLED)
2
G .735-G 739 S pecification
0
-2
-4 20log(Jout/Jin) (dB)
-6
X RT 82L24A P erform ance
-8
-10
-12
-14
10
2
10
3
10 (Freq.(MHz))
4
10
5
Receiver Jitter Transfer Function (Jitter Attenuator enabled)
Test Conditions: * Test Pattern 2^15-1 * Input Jitter 75% of Maximum Jitter Tolerance
FIGURE 24. JITTER ATTENUATION FUNCTION
10
0
IT U .G .736 M ask
-10
Jitter Attenuation (dB)
-20
-30
X RT 82L24A P erform ance
-40
-50
-60 0 10
10
1
10
2
10 (Freq.(MHz))
3
10
4
10
5
35
XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
ac
ORDERING INFORMATION
PART NUMBER XRT82L24AIV PACKAGE DISSIPATION PACKAGE 100 Lead TQFP (14 x 14 x 1.4mm) Theta-JA 38 C/W OPERATING TEMPERATURE RANGE -40C to +85C Theta-JC 6 C/W
PACKAGE DIMENSIONS 100 LEAD TQFP 14X14MM
D D1 75 51
76
50
D1
D
100
26
1
25
A2 e A Seating Plane A1
B C
L
NOTE: The control dimension is the millimeter column
INCHES SYMBOL A A1 A2 B C D D1 e L 0 MIN 0.055 0.002 0.053 0.007 0.004 0.622 0.547 MAX 0.063 0.006 0.057 0.011 0.008 0.638 0.555 MILLIMETERS MIN 1.40 0.05 1.35 0.17 0.09 15.80 13.90 MAX 1.60 0.15 1.45 0.27 0.20 16.20 14.10
0.020 BSC 0.018 0.030 7 0
0.50 BSC 0.45 0.75 7
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XRT82L24A
ac
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
REVISION HISTORY
REVISION 1.0.0 1.1.0 1.1.1 1.1.2 DATE 11/02 10/03 06/04 07/04 Initial issue Table 8 corrected PCLK frequency from 33MHz to16MHz and changed pulled down to pulled up. Figures 12 & 13 transformer ratio on Receive side changed from 2:1 to 1:2. Added the Manufacturing Mark on the Package Drawing. Changed Max power consumption for 100% Mark Density to 680 and 600 mW respectively for 75 and 120 Ohm Loads. DESCRIPTION
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet August 2004. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 37

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